期末考

001

module top; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, B);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F4, A ,c , d);

nand C2(F2, a, b, D);

nand C3(F3, B, c, d);

nand C4(F1, C, D); 

nand o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

1202

module top; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not S1(a, A);

not S2(b, B);

not S3(c, C);

not S4(d, D);

and C1(F4, A ,c , d);

and C2(F2, a, b, D);

and C3(F3, B, c, d);

and C4(F1, C, D); 

or o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

三位元加法器- 行為模式

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

1125

二位元加法器

module top;

wire [1:0]Sum, A, B;

wire Cout, Cin;

system_clock #400 clock(Cin);

system_clock #200 clock(A[0]);

system_clock #100 clock(B[1]);

system_clock #200 clock(B[0]);

system_clock #100 clock(A[1]);

adder2 M2(Cout, Sum, A, B, Cin);

endmodule

module adder2(Cout, Sum, A, B, Cin);

output Cout;

output [1:0]Sum;

input [1:0]A,B;

input Cin;

adder1 lo(C0,Sum[0], A[0], B[0], Cin);

adder1 hi(Cout, Sum[1], A[1], B[1],C0);

endmodule

//一位元加法器

module adder1(Cout, Sum, A, B, Cin);

output Cout, Sum;

input A,B,Cin;

not I1 (Anot, A);

not I2 (Bnot, B);

not I3 (Cinnot, Cin);

and I4 (L1, A, Cin);

and I5 (L2, Cin, B);

and I6 (L3, A, B);

and I7 (L4, Cinnot, A, Bnot);

and I8 (L5, Cin, A, B);

and I9 (L6, Cinnot, Anot, B);

and I10 (L7, Cin, Anot, Bnot);

or I11 (Cout, L1, L2, L3);

or I12 (Sum, L4, L5, L6, L7);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule

三位元加法器-結構模式

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor g1(s1, a, b);

xor g2(sum, s1, c_in);

and g3(c1, a,b);

and g4(c2, s1, c_in) ;

xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

1118

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 0+1+0=01 sum is WRONG!");

              else

               $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

                $display(" 0+1+1=10 sum is WRONG!");

              else

                $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 1+0+0=01 sum is WRONG!");

              else

               $display(" 1+0+0=01 sum is RIGHT!");

     carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 0) 

                $display(" 1+0+1=10 sum is WRONG!");

              else

                $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out != 1 | sum !== 0) 

               $display(" 1+1+0=10 sum is WRONG!");

              else

               $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display(" 1+1+1=11 sum is WRONG!");

              else

               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

module top;

wire Cout, Sum, A, B, Cin;

system_clock #400 clock1(Cin); 

system_clock #200 clock2(A);

system_clock #100 clock3(B);

adder1 M1(Cout, Sum, A, B, Cin);

endmodule

module adder1(Cout, Sum, A, B, Cin);

output Cout,Sum;

input A,B,Cin;

and I1 (AandB, A, B);

xor I2 (AxorB, A, B);

and I3 (And1, AxorB, Cin);

or I4 (Cout, AandB, And1);

xor I5 (Sum, AxorB, Cin);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

1104

1104

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