1202

module top; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not S1(a, A);

not S2(b, B);

not S3(c, C);

not S4(d, D);

and C1(F4, A ,c , d);

and C2(F2, a, b, D);

and C3(F3, B, c, d);

and C4(F1, C, D); 

or o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule